Referring to FIG. 1, a graph of data setup to write end time (Tsd) vs. probability of cell failure of a static random access memory (SRAM) is shown. The graph was generated by counting the number of failing cells on a bitmap. A small number of SRAM cells can require a larger (but within spec) Tsd (e.g., region 10 of FIG. 1). The SRAM cells that require the larger Tsd can fail during life testing. The time until failure can be as long as 500 hours of life testing. The SRAM cells fail due to poor contacts in cross-coupled latch transistors. If the defective cells can be detected during sort, the cells can be repaired.
A problem with testing the SRAM cells is that the average Tsd performance for a given die can vary substantially with process. If the silicon is “slow,” parts can be falsely rejected for having a large Tsd. Because of the variation, a tightly guardbanded test limit can result in a high yield loss. A more advanced and accurate tester is required to accurately define a narrow write enable pulse width that is varied depending on process corners. However, the testing of TSD timing cannot be performed at sort because testers that are accurate enough may not be available. Accurate testers can be made available, but historically have not been used to sort test because of cost issues. Even with an accurate tester, providing a variable test limit that tracks process variation is time consuming.
It would be desirable to have a device with a built-in self-timed test circuit that could compensate for process variation and predict cell failure prior to life testing of a given die.